Exemplary embodiments of the present invention relate generally to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor chip having a conductive protrusion formed therein to facilitate a test of a package, a semiconductor package using the same, and a method for manufacturing the same.
With broadening uses of miniaturized and high-performance electronic products such as mobile products, the efforts for miniaturized, high-capacity semiconductor memory devices continue. To improve the memory capacity, a plurality of semiconductor chips may be mounted and assembled in a single package. Packaging is generally considered to be more effective and less costly to increase storage capacity as compared to improving the degree of high integration in the semiconductor chip. Therefore, a variety of attempts to increase the storage capacity of a semiconductor memory device through a multi-chip package having a plurality of semiconductor chips therein are being made.
The multi-chip package may have a vertical configuration or a horizontal configuration. The vertical configuration comprises a plurality of semiconductor chips stacked vertically, and the through-silicon via (TSV) is one of the key technologies for this type of multi-chip package with high density and high performance. The package employing TSVs has a configuration that a plurality of semiconductor chips are coupled in a vertical direction through TSVs which are formed in the respective semiconductor chips at a wafer level.
A system in package (hereafter, referred to as SIP) is known as a package in which the same kind or various kinds of semiconductor devices are vertically stacked at a chip level or wafer level and the stacked wafers or chips are coupled to each other through TSVs. In such an SIP, the data storage density may be increased by stacking vertically the same kind of chips. Furthermore, various types of package may be manufactured by stacking various types of chips.
On the other hands, before the memory chips are stacked over the substrate, the performance of the memory chip needs to be tested. A memory chip includes a large number of bumps formed in a lower portion thereof, but the size and pitch of the bumps are very small. Therefore, a probe test is difficult to be performed.